Rethinking the GPU memory hierarchy
Repurposing idle GPU core resources as extra last-level cache, filtering shared and non-reusable data to curb LLC thrashing, hybrid 3D memory, off-chip shared memory, and a precharge-free DRAM architecture.
Four connected threads with one goal: AI and datacenter infrastructure that is more performant, efficient, scalable, and predictable.
Repurposing idle GPU core resources as extra last-level cache, filtering shared and non-reusable data to curb LLC thrashing, hybrid 3D memory, off-chip shared memory, and a precharge-free DRAM architecture.
Application-driven characterization of datacenter microbursts, web caching for the latency-constrained Internet, and session-persistent, hybrid stateful/stateless Layer-4 load balancing.
Ultra-fast, quorum-less coordination implemented directly on the wire, and fast encryption for communication between trusted execution enclaves.
Resource management for distributed binary neural networks on programmable data planes, hierarchical federated learning for large models on satellites, and reliability-aware scheduling for agentic LLM workflows.
I am particularly interested in co-designing the memory, network, and processing layers of future AI infrastructure, with academic and industry partners alike.